Background Art
In the synchronous semiconductor memory device disclosed in Japanese unexamined patent publication No. H11 (1999)-213668 (hereinafter referred to as “Patent Document 1”), a circuit shown in FIG. 9 is used as a control pulse generating circuit. It comprises an internal clock signal generator 150, a frequency divider 152, and a selector 153.
The internal clock signal generator 150 receives an external system clock signal CLK and generates an internal clock signal PCLK_DDR for a double data rate (DDR) operation mode having the same frequency as the external system clock signal CLK. The frequency divider 152 receives this internal clock signal PCLK_DDR, divides its frequency, and generates an internal clock signal PCKL_SDR for single data rate (SDR) operation mode having half the frequency of the internal clock signal PCLK_DDR.
The selector 153, in response to mode control signal/DDR, selects either one of internal clock signal PCLK_DDR for DDR operation mode or internal clock signal PCLK_SDR for SDR operation mode, and provides it as the internal clock signal PCLK.
When operating in DDR operation mode, the mode control signal /DDR has a low level. At this time, a DDR transmission switch 154 of the selector 153 is turned on in response to mode control signal/DDR and mode control signal/DDR inverted by an inverter 158, while a SDR transmission switch 156 is turned off. Therefore, internal clock signal PCLK_DDR for DDR operation mode is provided as the internal clock signal PCLK.
When operating in SDR operation mode, the mode control signal /DDR has a high level. At this time, the DDR transmission switch 154 of the selector 153 is turned off, and the transmission switch 156 is turned on, and internal clock signal PCLK_SDR for SDR operation mode is provided as the internal clock signal PCLK.
Problems to be Solved by the Invention
In the configuration depicted in Patent Document 1, the internal clock signal PCLK_DDR for DDR operation mode generated by the internal clock signal generator 150, and the internal clock signal PCLK_SDR for SDR operation mode provided from the frequency divider 152 are selected by the selector 153 and the internal clock signal PCLK is generated. In the selector 153, in response to the mode control signal/DDR and the signal from the inverter 158 providing its inverted signal, either one of the transmission switches 154, 156 is turned on while the other is turned off.
However, switching the operation mode between the SDR operation mode and the DDR operation mode depends on the transition of the logic level of the mode control signal/DDR. But since an operational delay may occur in the inverter 158 and transmission switches 154, 156, a time delay may occur between the transition of the mode control signal/DDR and the changeover of the internal clock signal PCLK.
In Patent Document 1, the counting of latency and the generation of various flags are controlled in response to the internal clock signal PCLK. It is necessary, therefore, to control the internal clock signal PCLK operating at double frequency by DDR operation mode and the load may be increased in this circuit configuration for handling the high speed clock.